The present disclosure relates to a field of design for testability of a circuit (e.g., a chip), and more specifically, to a test method and a test apparatus for testing a plurality of blocks in a circuit, the plurality of blocks having identical structures.
In order to improve circuit test efficiency, a hardware logic which may be used for testing a circuit is added into the circuit at a stage of designing the circuit, which is known as Design for Testability (DFT) of the circuit. Currently, a prevailing DFT method is a scan-based test method, which aims at identifying a manufacturing defect of a circuit (e.g., an undesirable short circuit or open circuit, etc.), rather than verifying a function of the circuit. In this method, when the circuit is designed, registers in the circuit are replaced with scan registers having scan input ports and scan output ports. When the circuit is tested, all the scan registers in the circuit may be connected into a scan chain. Then, excitation signals corresponding to one or more test patterns generated by an Automatic Test Pattern Generation (ATPG) tool are input to the scan chain, respectively. As known in the art, each test pattern can be used for testing, for example, one type of circuit defect, and includes an excitation signal to be applied to a circuit and an expected output response that should be generated in response to application of the excitation signal. Thus, by determining whether output responses of the scan chain are consistent with expected output responses corresponding to the respective test patterns, it can be determined whether the circuit has corresponding defects.
A plurality of blocks having identical structures (also referred to as reused blocks), such as intellectual property (IP) cores, neuron blocks in a cognitive computing circuit, etc., are often used in a designed circuit. As a scale of the circuit increases, a number of the blocks having the identical structures used in the circuit also increases. In existing DFT methods, these blocks are treated in the same way as other blocks, instead of adjusting the test methods for the circuit according to characteristics (i.e., “identical”) of these blocks, therefore test efficiency is not high.